1. Field of the Invention
The present invention pertains to the field of integrated circuit memory devices. More particularly, this invention relates to special testing modes for a shared page buffer resource in a flash memory device.
2. Background
A flash memory device contains a flash cell array for nonvolatile random access data storage in a computer system. Prior flash memory devices usually implement a write control circuit for programming and erasing areas of the flash cell array. The write control circuit typically programs the flash cells by applying a predetermined sequence of program level voltages to the flash cells.
A flash memory device may employ an on-chip programming data buffer to increase programming throughput to the flash cell array. The data buffer enables increased programming speed by buffering a set of programming data. The data buffer enables fast access to the programming data by the write control circuit. The fast access to the programming data enables the write control circuit to amortize the cycling of program level voltages across multiple bytes in the flash cell array.
In addition, a flash memory device may employ a multiple page interleaved programming data buffer to achieve further increases in programming throughput to the flash cell array. The interleaved programming data buffer enables an input/output driver to load one page while the write control circuit programs from another page. However, an interleaved programming data buffer increases the cost and complexity of flash memory device testing and diagnostics.